Article and specs

Atish Patra, Principal R&D Engineer, Western Digital
Anup Patel, Technologist, Western Digital

An Introduction to RISC-V Boot Flow

Slides for this presentation are available here:
https://content.riscv.org/wp-content/uploads/2019/12/Summit_bootflow.pdf

RISC-V Summit - December, 2019 - San Jose, California USA

Nice diagram with ring [ME = (-4) & (-3) ring] p.5